There are two main types of memory devices used in computers today, namely “non-volatile” and “volatile” memory devices. The name “non-volatile” comes from the fact that non-volatile memory devices maintain the data stored therein, even when power is removed or temporarily lost. It follows that the name “volatile” comes from the fact that volatile memory devices do not maintain the data stored therein when the power is removed or temporarily lost.
Common non-volatile memory devices include read only memory (ROM) devices, EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, and flash RAM devices. Common volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM) devices. Volatile memory devices have been widely used for temporary data storage, such as during data manipulation, since writing data into or reading data out of these devices can be performed quickly and easily. However, a disadvantage of these volatile memory devices is that they require the constant application of power, and in some cases a data refresh signal, to maintain data stored in the memory cells. Once power supplied to the device is interrupted, the data stored in the memory cells is lost.
Non-volatile memory devices suffer from an endurance problem caused by repeated cycling of program and erase operations, as well as slower access speeds than volatile memory devices. SRAM devices have a fast data access speed and a long lifetime, and are therefore suitable for use in a computer system. However, since SRAM is a volatile memory device, the stored data stored will be lost if power is interrupted. Therefore, there was a recognized need to back up information stored in SRAM memories in the event of power failure.
Consequently, non-volatile static random access memory (NVSRAM) has been developed, which pairs each SRAM cell with two EEPROM cells so as to produce a device capable of storing the contents of the SRAM cell in the event of power loss and then retrieving of those contents when power is restored. Each EEPROM cell is comprised of a floating gate transistor that has a charge placed on its floating gate to modify the voltage threshold VT of that floating gate transistor, and this charge indicates the state of the binary data retained in that EEPROM cell.
Reference is made FIG. 1 showing a conventional 10T (ten transistor) NVSRAM cell 10. The NVSRAM cell 10 includes a 6T (six transistor) SRAM cell 12 formed from first and second cross coupled inverters 14 and 16 forming a latch that stores a data bit, with pass gate transistors MN3 and MN4 providing access to the stored data bit. First and second EEPROM strings 17 and 18 serve to back up the stored data bit if power loss is anticipated or expected, and then the data bit can be retrieved once power is restored.
The first inverter 14 is formed from PMOS transistor MP1 and NMOS transistor MN1. Transistor MP1 has its source coupled to the power supply line PS and its body coupled to the n-well line NW. Transistor MN1 has its drain coupled to the drain of transistor MP1, its source coupled to the NS line, and its gate coupled to the gate of transistor MP1.
The second inverter 16 is formed from PMOS transistor MP2 and NMOS transistor MN2. Transistor MP2 has its source coupled to the power supply line PS and its body coupled to the n-well line NW. Transistor MN2 has its drain coupled to the drain of transistor MP2, its source coupled to the NS line, and its gate coupled to the gate of transistor MP2. The gates of transistors MP2 and MN2 are coupled to the drains of transistors MP1 and MN1, and the gates of transistors MP1 and MN1 are coupled to the drains of transistors MP2 and MN2.
Pass gate NMOS transistor MN3 has its drain coupled to node N1 (at the drains of transistors MP1 and MN1), its source coupled to the bit line BL, and its gate coupled to the word line WL. Pass gate NMOS transistor MN4 has its drain coupled to node N2 (at the drains of transistors MP2 and MN2), its source coupled to the complementary bit line BLC, and its gate coupled to word line WL.
The first EEPROM string 17 is comprised of NMOS transistor MN5 in series with floating gate transistor EEL The transistor MN5 has its drain coupled to node N1 and a gate coupled to the reload line RL. The floating gate transistor EE1 has its drain coupled to the source of transistor MN5, its source coupled to the EEPROM source line EES, and its gate coupled to the control gate line CGL.
The second EEPROM string 18 is comprised of NMOS transistor MN6 in series with floating gate transistor EE2. The transistor MN6 has its drain coupled to node N2 and its gate coupled to the reload line RL, and a source. The floating gate transistor EE2 has its drain coupled to the source of transistor MN6 and its source coupled to the EEPROM source line EES.
Operation of this circuit for writing data into and reading data from the SRAM cell 12 during standard operation is well known in the art and need not be described herein.
The storing of non-volatile data into the EEPROM cells (floating gate transistors EE1 and EE2) is accomplished by performing an erase operation followed by a program operation.
The erase operation operates as follows. The EES, NS, WL and RL lines are set to a logic low, isolating the floating gate transistors EE1 and EE2 from the SRAM 12. The n-well line NW and power supply line PS are set to VDD. The CGL line is then pulsed with a high voltage, for example 14V, erasing the contents of the floating gate transistors EE1 and EE2, putting them into an off state.
The program operation operates as follows. The EES, NS, WL, and RL lines are set to a logic low, while the n-well line NW is set to VDD and the power supply line PS is set to 5V. The CGL line is pulsed with −9V so that a cell storing a one sees 5-(−9)=14V and a cell storing a zero sees 0-(−9)=9V, while the RL line is then set to a logic high to connect the floating gate transistors EE1 and EE2 to the SRAM 12. The inverter 14 or 16 that is holding a logic high passes the logic high to the floating gate transistor EE1 or EE2 connected thereto, and the inverter 14 or 16 that is holding a logic zero passes the logic low to the floating gate transistor EE1 or EE2 connected thereto. While 14V at CGL is sufficient to program an EEPROM cell, 9V has a negligible effect and is insufficient to program an EEPROM cell. Therefore, the floating gate transistor EE1 or EE2 receiving a logic one is programmed, while the floating gate transistor EE1 or EE2 receiving a logic zero is not programmed. Thus, the data from the SRAM cell 12 is stored as non-volatile data.
The reloading of non-volatile data into the SRAM cell 12 upon power-up is as follows. The EEPROM source line EES and NS line are placed at a logic low, as is the word line WL. The CGL line is placed at a reference voltage Vref, typically around 0.5V to 1V. The n-well line NW and RL line are placed at VDD. The power supply line PS then ramps up. The RL line being at VDD turns on transistors MN5 and MN6, coupling the EEPROM cells (floating gate transistors EE1 and EE2) to nodes N1 and N2. The floating gate transistors EE1 and EE2 will be at different states, with one being “programmed” and containing the bit of stored data and the other being “erased”. The floating gate transistor EE1 or EE2 that is programmed will draw more current than the one that is erased, which unbalances the cross coupled inverters 14 and 16, resulting in a flipping of the states of the inverters 14 and 16 to match that of the floating gate transistors EE1 and EE2, thereby reloading the SRAM cell 12 with the stored non-volatile data bit.
This NVSRAM cell 10 design is functional in ideal conditions. However, operating conditions are often less than ideal. The flipping of the states of the inverters 14 and 16 is controlled by the differential conductivity of the floating gate transistors EE1 and EE2. In an ideal case, the erased floating gate transistor EE1 or EE2 draws little to no current, while the programmed floating gate transistor EE1 or EE2 draws substantially more current than the erased floating gate transistor EE1 or EE2, facilitating the flip. However, in the non-ideal cases often present in real devices, both floating gate transistors EE1 and EE2 will draw some current. This may cause a current surge on the power supply during a reload operation. If multiple cells are reloaded at once, and total current surge prevents the power supply line PS from rising properly, this would leave the cells in metastable conditions, resulting in data corruption and chip malfunction. Another error may occur where both floating gate transistors EE1 and EE2 draw insufficient current, with the result being the length of time for the inverters 14 and 16 to flip becoming undesirable, or the inverters 14 and 16 in some cases not flipping.
In an attempt to mitigate these issues, some NVSRAM cells operate by reloading the SRAM cells in subgroups from the EEPROM cells upon powerup. However, the total time to perform this is on the order of tens of miliseconds, during which time the chip is not ready for use. This is not desirable. Therefore, further development is needed.